DocumentCode
2233375
Title
A staged carry-save-adder array for Montgomery modular multiplication
Author
Wang, Jhing-Fa ; Lin, Po-Chuan ; Chiu, Ping-Kun
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
2002
fDate
2002
Firstpage
97
Lastpage
100
Abstract
In this paper, an efficient VLSI architecture to compute the n-bit Montgomery modular multiplication is proposed. By using the staged carry save adder (CSA) array, the computation cycles of addition reduced by about 3n/8. In addition, we apply the switch unit to save 2Q-2 registers from the traditional Q-bit CSA. Compare with the original method, the total clock cycles can be reduced by 68% in the case of n=1024 and Q=512 bits.
Keywords
VLSI; adders; carry logic; computational complexity; digital arithmetic; integrated circuit design; logic design; multiplying circuits; public key cryptography; shift registers; 1024 bit; 512 bit; CSA array; CSA registers; Montgomery modular multiplication; RSA cryptosystem; VLSI architecture; addition computation cycles; clock cycles; public-key cryptosystem; staged carry-save-adder array; switch unit; Cities and towns; Clocks; Computer architecture; Costs; Data security; Digital signatures; Hardware; Modems; Public key cryptography; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on
Print_ISBN
0-7803-7363-4
Type
conf
DOI
10.1109/APASIC.2002.1031541
Filename
1031541
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