DocumentCode
2233528
Title
High Throughput High Performance NoC Switch
Author
el ghany, M. ; El-Moursy, Magdy A. ; Ismail, Mohamed
Author_Institution
Electron. Eng. Dept., German Univ. in Cairo, Cairo, Egypt
fYear
2008
fDate
16-17 Nov. 2008
Firstpage
237
Lastpage
240
Abstract
Increasing the number of virtual channels can improve the throughput in an on-chip interconnection network. High throughput butterfly fat tree (HTBFT) architecture to achieve high performance networks on chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to butterfly fat tree switch.
Keywords
integrated circuit interconnections; network-on-chip; high throughput butterfly fat tree architecture; high throughput high performance NoC switch; networks-on-chip; on-chip interconnection network; virtual channels; Delay; Electronic mail; Frequency; Graphics; Integrated circuit interconnections; Multiprocessor interconnection networks; Network-on-a-chip; Switches; Throughput; Tree graphs; BFT; Latency; NoC; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
NORCHIP, 2008.
Conference_Location
Tallinn
Print_ISBN
978-1-4244-2492-4
Electronic_ISBN
978-1-4244-2493-1
Type
conf
DOI
10.1109/NORCHP.2008.4738319
Filename
4738319
Link To Document