A new direction in ASIC high-performance clock methodology

This paper describes an effective clock methodology for growing and inserting clock trees on high-performance, low-power ASIC chips. Key attributes of the method are that it does not add unnecessary wire, avoids the noise and power-supply drop associated with localized high-current-density clock circuits, and accounts for high-frequency effects such as inductance. A sophisticated automated balanced router and a special clock buffer circuit allow the methodology to work on a large variety of chip sizes, package types, latch counts, and operating frequencies. The methodology enabled automated creation of entire clock networks, including verification, in less than one day, with less than 100 ps of design system skew on complex ASIC chips