VAMP: a VHDL based concept for accurate modeling and post layout timing simulation of electronic systems

This paper presents a new concept for accurate modeling and timing simulation of electronic systems integrated in a typical VHDL design environment, taking into account the requirements of deep submicron technology. Contrary to conventional concepts, autonomous models for gates and interconnections are used. A piece-wise-linear signal representation allows to model waveform dependent effects. Furthermore, the gate models catch pattern dependencies, the models of interconnections take into account post layout information with ramified structure, different layers and even contact holes