A pipelined systolic architecture for the hardware oriented region based motion estimation algorithm

Motion estimation is a fundamental step for high quality, low bandwidth video compression. Recently the MPEG-4 group has proposed some low complexity algorithms. They have almost the same performance in term of PSNR of the Full Search algorithm, but at the same time the complexity is dramatically reduced. However it is difficult to realize these algorithms with conventional hardware structures. For this reason we presented a Hardware Oriented Region Based algorithm (HORB) with similar performances, but that can be implemented with a simple hardware structure. Here we present an architecture tailored to meet the design constraint of the HORB algorithm (and at the same time capable of realizing the Full Search algorithm).