Low power design of a multi-mode transceiver

Author

Soudris, D. ; Perakis, M. ; Mizas, X. ; Mardiris, V. ; Katis, K. ; Dre, C. ; Tzimas, A.E. ; Metaxakis, E.G. ; Kalivas, G. ; Zervas, N. ; Theoharis, S. ; Theodoridis, G. ; Thanailakis, A. ; Goutis, C.

Author_Institution

Dept. of Electr. & Comput. Eng., Democritus Univ. of Thrace, Xanthi, Greece

Volume

2

fYear

2000

fDate

2000

Firstpage

721

Abstract

Recent advances in electronic technology integration coupled with increasing needs for more services in portable communications favors the development of high performance dual-mode terminals. We present the complete architecture implementation of the GMSK/GFSK modulator/demodulator including the FIR filters design. The main features of the modulator/demodulator and the architectural implementation of FIR filters are described. The interface with ASPIS processor and A/D & D/A converters is also described in detail manner. The whole architecture of the modulator/demodulator was described by VHDL hardware language, synthesised and implemented in Xilinx environment

Keywords

FIR filters; cellular radio; cordless telephone systems; demodulators; digital radio; frequency shift keying; low-power electronics; minimum shift keying; modulators; transceivers; A/D converters; ADC; ASPIS processor interface; D/A converters; DAC; DECT standard; FIR filter design; GMSK/GFSK modulator/demodulator; GSM standard; VHDL hardware language; Xilinx environment; architecture implementation; high performance dual-mode terminals; low power design; multi-mode transceiver; Clocks; Demodulation; Digital modulation; Digital-analog conversion; Finite impulse response filter; GSM; Signal processing; Testing; Transceivers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International Symposium on

Conference_Location

Geneva

Print_ISBN

0-7803-5482-6

Type

conf

DOI

10.1109/ISCAS.2000.856430

Filename

856430