A new router for reducing “antenna effect” in ASIC design

In this paper, an efficient router for reducing “antenna effect” damage is reported. The antenna effect is a phenomenon of gate-oxide degradation by charge buildup on conductors in plasma-based manufacturing processes. It directly influences yield and reliability of VLSIs. The amount of the degradation is a direct function of interconnect geometry (e.g., amount of floating conductors connecting to the gate oxide during the processes). The proposed router combines a traditional router and a modification of wires for reducing the antenna effect damage using a rip-up and reroute method. It reduces the damage with only a small penalty of die size and performance. The effectiveness of the router, which is implemented in the layout system HGALOP, is demonstrated by experimental results on 3-4 level metal industrial sea-of-gates (SOG) circuits