CMOS VCO-prescaler cell-based design for RF PLL frequency synthesizers

Cell-based design using a new D-latch is employed to design a VCO and prescaler for RF PLL frequency synthesizers using a standard 0.5 μm CMOS process and 3.3 V supply. The divide-by 64/65 dual-modulus prescaler has a maximum operating frequency of 1.6 GHz and dissipates 9 mW. The VCO is a single-stage ring oscillator with a maximum frequency of 2.2 GHz and consumes 20 mW. The VCO and prescaler combination operates at a maximum frequency of 1.6 GHz and consumes 56 mW