A 64 bit parallel CMOS adder for high performance processors

A fast 64 bit parallel binary adder for high performance microprocessors and DSP processors is described. It is implemented in UMC 2.5 V 0.25 μm 1-poly 5-metal CMOS technology. A new adder architecture with four stages of dynamic logic is proposed, based on the modification of Kogge and Stone algorithm. Efficiently using dynamic compound gates, clock-delayed dynamic logic and FET scaling technique, the new adder architecture achieved good performance. The addition latency is 700 ps, 20% faster than that of the conventional architecture adder. The area of the adder is 0.16 mm², similar to that of the conventional one.