DocumentCode :
2234076
Title :
A new floating-point normalization scheme by bit parallel operation of leading one position value
Author :
Han, Kyung-Nam ; Han, Sang-Wook ; Yoon, Euisik
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea
fYear :
2002
fDate :
2002
Firstpage :
221
Lastpage :
224
Abstract :
In this paper, a new normalization design method for a floating-point unit is presented. Shift amount information for normalization is devised to generate leading one position value (LOPV). LOPV is the number with all zero bits except the leading one position. LOPV can be easily generated by two NOR planes, which implies it can be implemented by bit-parallel operations. Therefore, LOPV can be acquired within about a half delay time of conventional leading zero counters (LZC). An additional NOR plane is required to decode the LOPV to shifter control signals. A total of three NOR planes and an actual shifter operation can implement the floating-point normalization. The chip has been fabricated by using a commercial TSMC 0.18 μm 5-metal CMOS technology with 1.8 V supply voltage. The core area is 550 μm × 200 μm and normalization delay has been measured as 1.4 ns.
Keywords :
CMOS digital integrated circuits; floating point arithmetic; microprocessor chips; 0.18 micron; 1.4 ns; 1.8 V; 200 micron; 550 micron; CMOS processor; NOR plane; TSMC 5-metal CMOS technology; bit parallel operation; floating-point normalization scheme; floating-point unit; leading one position value; shifter control signals; Area measurement; CMOS technology; Counting circuits; Decoding; Delay effects; Design methodology; Optimization methods; Semiconductor device measurement; Signal generators; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-7363-4
Type :
conf
DOI :
10.1109/APASIC.2002.1031572
Filename :
1031572
Link To Document :
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