Power efficient MPEG-4 decoder architecture featuring low-complexity error resilience

Author

Byun, H.I. ; Jeon, M.Y. ; Seo, J.Y. ; Lee, K.W. ; Lee, S.H. ; Kang, B.H.

Author_Institution

Semicond. Lab., C & S Technol. Inc., Seoul, South Korea

fYear

2002

fDate

2002

Firstpage

225

Lastpage

228

Abstract

A media processor supporting MPEG-4 SP@LI and H.263 baseline has been developed. This processor includes a RISC core, dedicated video decoding hardware, audio/voice decoder, post processor, and some peripherals. In order to increase flexibility and reduce power dissipation, separated bus architecture, which may minimize the bus transaction, is adopted. An enhanced error resiliency is also equipped for error-prone environment, and additional innovative low-power design techniques are applied for portable applications. This processor was integrated in a 0.25μm CMOS PLM process and contains 900K gates on 45mm² die with 50mW power dissipation at 27MHz.

Keywords

CMOS digital integrated circuits; audio signal processing; decoding; low-power electronics; multimedia communication; reduced instruction set computing; video signal processing; 0.25 micron; 27 MHz; 50 mW; CMOS PLM process; H.263 baseline; MPEG-4 decoder architecture; RISC core; SP@LI; audio/voice decoder; bus transaction; dedicated video decoding hardware; error resiliency; error-prone environment; low-complexity error resilience; low-power design techniques; multimedia data; portable applications; power dissipation; separated bus architecture; Clocks; Codecs; Coprocessors; Decoding; Energy consumption; MPEG 4 Standard; Process control; Reduced instruction set computing; Resilience; SDRAM;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031573

Filename

1031573