A low power, wide operating frequency and high noise immunity half-digital phased-locked loop

Author

Cheng, Kuo-Hsing ; Yang, Wei-Bin

Author_Institution

Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan

fYear

2002

fDate

2002

Firstpage

263

Lastpage

266

Abstract

In this paper, a low power, wide operating frequency and high noise immunity half-digital phase locked loop (HDPLL) is proposed and analyzed. A novel voltage-controlled oscillator (VCO) is proposed and used to improve linear V-f characteristic and reduce the total power consumption for the HDPLL design. By HSPICE simulation results, the power dissipation of the novel VCO can be reduced over 50% in comparison to conventional VCO. Moreover, the novel VCO also has good immunity in noises and wide operating frequencies.

Keywords

SPICE; VLSI; circuit simulation; digital phase locked loops; integrated circuit noise; radiofrequency integrated circuits; voltage-controlled oscillators; HDPLL; HSPICE simulation results; VLSI; half-digital phased-locked loop; linear V-f characteristic; low power circuit; noise immunity; operating frequency; radiofrequency integrated circuits; total power consumption; voltage-controlled oscillator; Circuit noise; Filters; Frequency; Jitter; Phase detection; Phase locked loops; Phase noise; Power dissipation; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031582

Filename

1031582