DocumentCode
2234349
Title
Combined transistor sizing with buffer insertion for timing optimization
Author
Jiang, Yanbin ; Sapatnekar, Sachin S. ; Bamji, Cyrus ; Kim, Juho
Author_Institution
Dept. of Electr. Comput. Eng., Iowa State Univ., Ames, IA, USA
fYear
1998
fDate
11-14 May 1998
Firstpage
605
Lastpage
608
Abstract
This paper presents strategies to insert buffers in a circuit, combined with gate sizing, to achieve better power-delay and area-delay tradeoffs. The delay model incorporates placement-based information and the effect of input slew rates on gate delays. The results obtained by using the new method are significantly better than the results given by merely using a TILOS-like transistor sizing algorithm alone
Keywords
CMOS logic circuits; buffer circuits; circuit optimisation; combinational circuits; delays; logic simulation; timing; area-delay tradeoffs; buffer insertion; gate delays; input slew rates; placement-based information; power-delay tradeoffs; timing optimization; transistor sizing; Capacitance; Combinational circuits; Coupling circuits; Delay effects; Design optimization; Inverters; Power system modeling; Semiconductor device modeling; Threshold voltage; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1998. Proceedings of the IEEE 1998
Conference_Location
Santa Clara, CA
Print_ISBN
0-7803-4292-5
Type
conf
DOI
10.1109/CICC.1998.695051
Filename
695051
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