Title :
Delay-difference DLL and its-application on skewed output buffer
Author :
Tsao, Ya-Lan ; Chung, Ming-Chao ; Jou, Shyh-Jye
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-li, Taiwan
Abstract :
The delay-locked loop (DLL) is the key element to reduce clock skew, and provide multiple clock phases. In this paper, a DLL based upon self-biased techniques is designed. Then an improved 2D array DLL is proposed, based on the 1D DLL. Also, a new 3D DLL structure is proposed. The DLL is fabricated with 2 V 0.35 μm CMOS technology, and the measurement results shows that the peak to peak jitter at 340 MHz is 24 ps. To reduce the noise caused by the simultaneously switched output (SSO), we used a DLL array to skew the switching time of the SSO. A 36 phase improved DLL array with 10 SSOs is fabricated with 2 V 0.35 μm CMOS technology. Measurement results show that the Vdd/GND voltage bounce is improved by 65% and the rise time of output signals is improved from 1000 ps to 530 ps.
Keywords :
CMOS digital integrated circuits; SPICE; buffer circuits; circuit CAD; circuit simulation; clocks; delay lock loops; integrated circuit design; integrated circuit measurement; integrated circuit modelling; integrated circuit noise; logic CAD; logic simulation; timing jitter; 0.35 micron; 1000 ps; 1D DLL; 2 V; 24 ps; 2D array DLL; 340 MHz; 530 ps; CMOS delay-difference DLL; CMOS technology; DLL arrays; DLL self-biased techniques; HSPICE simulations; SSO switching time; Vdd/GND voltage bounce; clock skew reduction; delay-locked loops; multiple clock phases; output signal rise time; peak to peak jitter; simultaneously switched output noise reduction; skewed output buffer applications; CMOS technology; Clocks; Delay; Fluctuations; Frequency; Inductance; Jitter; Noise reduction; Phased arrays; Voltage;
Conference_Titel :
ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on
Print_ISBN :
0-7803-7363-4
DOI :
10.1109/APASIC.2002.1031586
