DocumentCode :
2234377
Title :
Efficient architecture and implementations of AES
Author :
Chen, Dong ; Shou, Guochu ; Hu, Yihong ; Guo, Zhigang
Author_Institution :
Sch. of Inf. & Commun. Eng., Beijing Univ. of Posts & Telecommun. (BUPT), Beijing, China
Volume :
6
fYear :
2010
fDate :
20-22 Aug. 2010
Abstract :
An equivalent optimized sub-pipelined architecture is proposed to implement the AES, every round including encryption and decryption needs one clock cycle. The SubBytes/InvSubBytes operation using composite field arithmetic in GF(24) and BlockRAMs respectively. In addition, an efficient key expansion which supports the output of 128 bits key per cycle and allows key changes every cycle is also presented. The novel pipelined design can achieve a throughput of 82.65Gbps on a Xilinx Virtex-4 xc4vlx100 device with composite field implementation of the SubBytes operation. By using 40 BlockRAMs and 8901 slices, the throughput of 64 Gbps is achieved with a frequency of 500MHz.These two designs´ throughput/area rate are all over 6 Mbps/Slice indicate that our designs are low-cost for high-speed implementation.
Keywords :
cryptography; parallel architectures; pipeline processing; random-access storage; AES; SubBytes-InvSubBytes operation; Xilinx Virtex-4 xc4vlxl00 device; blockRAMs; clock cycle; composite field arithmetic; decryption; encryption; equivalent optimized sub-pipelined architecture; frequency 500 MHz; key expansion; CMOS integrated circuits; Clocks; Cryptography; Field programmable gate arrays; Performance evaluation; Registers; Throughput; AES; FPGA; KeyExpansion; composite field; sub-pipelined;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Advanced Computer Theory and Engineering (ICACTE), 2010 3rd International Conference on
Conference_Location :
Chengdu
ISSN :
2154-7491
Print_ISBN :
978-1-4244-6539-2
Type :
conf
DOI :
10.1109/ICACTE.2010.5579818
Filename :
5579818
Link To Document :
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