Design and implementation of a scalable fast Fourier transform core

Author

Sung, Cheng-Han ; Lee, Kun-Bin ; Jen, Chein-Wei

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2002

fDate

2002

Firstpage

295

Lastpage

298

Abstract

A novel approach for scalable length Fast Fourier Transform (FFT) in single Processing Element (single PE) architecture has been developed. The scalable length FFT design meets the different lengths requirement of FFT operation in an OFDM system. An efficient mechanism, named Interleaved Rotated Data Allocation (IRDA), to replace the multiple-port memory with a single-port memory has also been proposed. Using a single-port memory instead of multiple-port memory makes the design more area efficient.

Keywords

CMOS digital integrated circuits; OFDM modulation; digital signal processing chips; fast Fourier transforms; parallel memories; telecommunication computing; DSP chip; OFDM system; TSMC CMOS lP4M process; interleaved rotated data allocation; multiple single-port memories; scalable FFT core; scalable fast Fourier transform core; scalable length FFT; single PE architecture; single processing element architecture; Costs; Digital signal processing; Digital video broadcasting; Fast Fourier transforms; Fourier transforms; Hardware; Lungs; OFDM; Signal processing; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031590

Filename

1031590