Design and implementation of an acoustic echo canceller

In this paper the AEC (acoustic echo canceller) is designed and implemented using VHDL. The designed echo canceller employs a pipeline and master-slave structure, and is realized with FPGA. As an adaptive algorithm, the normalized LMS algorithm is used. For coefficient adjustment, the stochastic iteration algorithm (SIA) which uses only current residual values is used and the number of registers are evidently reduced and convergence speed is also much improved compared to existing methods by using an embedded array block of FPGA for the FIR filter structure of the transceiver. The designed echo canceller is verified with the test board implemented for this paper. With the top-down design and synthesis using VHDL, the design time is reduced and modular design is achieved.