A low-power Reed-Solomon decoder for STM-16 optical communications

Author

Hsie-Chia Chang ; Lin, Chien-Ching ; Lee, Cheti-Yi

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2002

fDate

2002

Firstpage

351

Lastpage

354

Abstract

In this paper, a low-power Reed-Solomon (RS) decoder for STM-16 optical communications is presented. It mainly contains one (255,239) RS decoder and four 2 K-bit embedded memory for correcting the received codewords. Except the novel syndrome calculator reducing half the syndrome computations, our proposal also features a modified Berlekamp-Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The (255,239) RS decoder is implemented by 0.25 μm CMOS 1P5M standard cells with gate counts of 32.9 K and area of 2.03 mm². Simulation results show our approach can work successfully at the data rate of 2.5-Gbps and achieve 80% reduction of power dissipation on the average.

Keywords

CMOS integrated circuits; Reed-Solomon codes; circuit simulation; decoding; error correction codes; low-power electronics; optical communication equipment; 0.25 micron; 2 kbit; 2.5 Gbit/s; CMOS 1P5M standard cells; Chien search circuit terminated mechanism; RS decoder; STM-16 optical communications; data rate; embedded memory; gate counts; key equation solver; low-power Reed-Solomon decoder; modified Berlekamp-Massey algorithm; power dissipation; received codewords; simulation; syndrome calculator; syndrome computation; Circuit simulation; Computational modeling; Decoding; Energy consumption; Equations; Optical fiber communication; Polynomials; Power dissipation; Proposals; Reed-Solomon codes;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031604

Filename

1031604