Title :
Design and development of FPGA based adaptive thresholder for image processing applications
Author :
Sultana, Azeema ; Meenakshi, M.
Author_Institution :
VLSI Design & Embedded Syst., Dr. Ambedkar Inst. of Technol., Bangalore, India
Abstract :
This paper presents design, implementation and real time validation of Image binarization process using weight based clustering algorithm, which uses the clustering property of neural network. The generic technique for image binarization requires choosing a threshold value and comparing the pixel values with the threshold and classifying as black and white. The proposed algorithm calculates a global optimum threshold by learning from the image background and foreground features. A simple two-weight neural network is implemented to cluster the foreground and background pixels. Here an adaptive thresholding technique based on competitive learning is selected for Weight Updating. The developed algorithm is implemented on a FPGA platform hardware system, which consists of two functional blocks. The first block is used to obtain the threshold value for the image frame; another block to apply the threshold value to the frame. This parallelism and the simple hardware component of both blocks make this approach suitable for real-time applications, while the performance remains comparable with the Otsu technique frequently used in off-line threshold determination. Results from the proposed algorithm are presented for numerous examples, both from simulations and experimentally using the FPGA.
Keywords :
field programmable gate arrays; image segmentation; learning (artificial intelligence); neural nets; pattern clustering; FPGA based adaptive thresholder; Otsu technique; background pixels; competitive learning; foreground pixels; global optimum threshold; image binarization process; image processing applications; threshold value; two-weight neural network; weight based clustering algorithm; weight updating; Algorithm design and analysis; Entropy; Field programmable gate arrays; Hardware; Histograms; Image edge detection; Real time systems; Adaptive thresholding; FPGA implementation; Real-time thresholding; neural network;
Conference_Titel :
Recent Advances in Intelligent Computational Systems (RAICS), 2011 IEEE
Conference_Location :
Trivandrum
Print_ISBN :
978-1-4244-9478-1
DOI :
10.1109/RAICS.2011.6069387