VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems

Author

Hsu, Huai-Yi ; Wu, An-Yeu

Author_Institution

Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2002

fDate

2002

Firstpage

359

Lastpage

362

Abstract

This paper presents the VLSI design of a reconfigurable multimode Reed Solomon (RS) codec for various high-speed communication systems. Our decoder design is based on the Euclidean algorithm such that the datapath units are regular and simple. With its ability to support a variety of (n, k, t) RS specifications (0≤t≤8) and (0≤n≤255), this RS codec design is suitable for multi-mode systems such as the xDSL and the cable modem systems. The chip operates at a clock frequency of 100 MHz and has a data processing rate of 800 Mbits/s in 0.35 μm CMOS technology at the supply voltage of 3.3 V. The total gate count is 34,647 gates and the core size is only 1,578 × 1,560 μm².

Keywords

CMOS digital integrated circuits; Reed-Solomon codes; VLSI; codecs; digital subscriber lines; forward error correction; modems; (n, k, t) RS specifications; 0.35 micron; 100 MHz; 3.3 V; 800 Mbit/s; CMOS; Euclidean algorithm; VLSI design; cable modem systems; data processing rate; datapath units; high-speed communication systems; reconfigurable multi-mode Reed-Solomon codec; total gate count; xDSL; Algorithm design and analysis; CMOS technology; Clocks; Codecs; Data processing; Decoding; Frequency; Modems; Reed-Solomon codes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031606

Filename

1031606