Title :
Self-testing of FPGA delay faults in the system environment
Author :
Krasniewski, Andrzej
Author_Institution :
Inst. of Telecommun., Warsaw Univ. of Technol., Poland
Abstract :
We propose a procedure for self-testing of an FPGA programmed to implement a user-defined function. The procedure is intended to improve the detectability of FPGA delay faults. This improvement is obtained by modifying the functions of LUTs in the section under test, so that each LUT implements a XOR function. We show that, despite many potential problems, the proposed modification can significantly enhance the susceptibility of FPGA delay faults to random testing
Keywords :
automatic testing; delays; fault location; field programmable gate arrays; integrated circuit testing; logic testing; table lookup; FPGA delay faults; FPGA testing; LUT-based FPGAs; XOR function; random testing; self-testing; system environment; user-defined function; Automatic testing; Built-in self-test; Delay; Field programmable gate arrays; Table lookup; Test pattern generators;
Conference_Titel :
On-Line Testing Workshop, 2000. Proceedings. 6th IEEE International
Conference_Location :
Palma de Mallorca
Print_ISBN :
0-7695-0646-1
DOI :
10.1109/OLT.2000.856610
