A VLSI architecture of DMT based transceiver for VDSL system

Author

Chang, Ching-Chi ; Shieu, Muh-Tian ; Wang, Chorng-Kuang

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

fYear

2002

fDate

2002

Firstpage

363

Lastpage

366

Abstract

This paper presents a VLSI architecture of the transceiver for DMT-VDSL system with data rate as high as 52 Mbps. Consisting of four radix-2 stages and three radix2/4/8 stages, a variable length pipelined architecture of FFT/IFFT compatible with 5 modes is proposed to perform the DMT modulation/demodulation. Based on LMS adaptation algorithm, time domain equalizer (TEQ) and frequency domain equalizer (FEQ) are built. The former makes SSNR > 40dB in the steady-state, while the latter performs 11-bit accuracy. Moreover, timing recovery is adopted to compensate ±200 ppm symbol rate offset. The RTL simulation shows that the design achieves 52 Mbps transmission in short channel model and 16 Mbps for long channel environment.

Keywords

VLSI; digital subscriber lines; equalisers; least mean squares methods; parallel architectures; pipeline processing; synchronisation; 11 bit; 16 Mbit/s; 52 Mbit/s; DMT based transceiver; LMS adaptation algorithm; SSNR; VDSL; VLSI architecture; frequency domain equalizer; long channel environment; radix-2 stages; short channel model; symbol rate offset; time domain equalizer; timing recovery; variable length pipelined architecture; Crosstalk; DSL; Data engineering; Least squares approximation; OFDM modulation; Radio broadcasting; Radiofrequency interference; Transceivers; Transmitters; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2002. Proceedings. 2002 IEEE Asia-Pacific Conference on

Print_ISBN

0-7803-7363-4

Type

conf

DOI

10.1109/APASIC.2002.1031607

Filename

1031607