A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000

Author

Pastuszak, Grzegorz

Author_Institution

Inst. of Radioelectron., Warsaw Univ. of Technol.

fYear

2005

fDate

6-6 July 2005

Firstpage

225

Lastpage

228

Abstract

The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is dedicated to generate two context-symbol pairs per clock cycle. A novel method called dynamic significance state restoring (DSSR) allows reduction of on-chip memories. The overall design is described in VHDL and synthesized for FPGA and ASIC technologies. Simulation results show that for FPGA Stratix devices, the engine can process about 22 million samples at the frequency of 66 MHz

Keywords

application specific integrated circuits; block codes; data compression; field programmable gate arrays; hardware description languages; image coding; memory architecture; pipeline processing; 66 MHz; ASIC technology; BPC; DSSR method; FPGA Stratix device; JPEG 2000; VHDL; application-specific integrated circuit; bit-plane coder; context-symbol pair generation; dynamic significance state restoring; embedded block coding algorithm; field programmable gate array; hardware description language; on-chip memory architecture; pipeline structure; Application specific integrated circuits; Block codes; Clocks; Decision support systems; Field programmable gate arrays; Image coding; Image restoration; Memory architecture; Pipelines; Transform coding;

fLanguage

English

Publisher

ieee

Conference_Titel

Multimedia and Expo, 2005. ICME 2005. IEEE International Conference on

Conference_Location

Amsterdam

Print_ISBN

0-7803-9331-7

Type

conf

DOI

10.1109/ICME.2005.1521401

Filename

1521401