Title :
Oscillation control in logic simulation using dynamic dominance graphs
Author_Institution :
Dept. of Comput. Eng., Chalmers Univ. of Technol., Goteborg, Sweden
Abstract :
Logic-level modeling of asynchronous circuits in the presence of races frequently gives rise to oscillation. A new method for solving oscillation occurring in feedback loops (FLs) is presented. First, a set of graph traversal algorithms is used to locate the FLs and order them with respect to a dominance relation. Next, a sequence of resimulations with the feedback vertices forced into stable states is performed. The proposed method can handle noncritical races occurring in asynchronous circuits and has applications in feedback bridging fault simulation
Keywords :
asynchronous circuits; circuit analysis computing; hazards and race conditions; logic CAD; asynchronous circuits; dynamic dominance graphs; fault simulation; feedback loops; graph traversal algorithms; logic simulation; races; resimulations; Adders; Asynchronous circuits; Circuit faults; Circuit simulation; Computational modeling; Context modeling; Feedback loop; Logic; Permission; Switches;
Conference_Titel :
Design Automation Conference Proceedings 1996, 33rd
Conference_Location :
Las Vegas, NV
Print_ISBN :
0-7803-3294-6
DOI :
10.1109/DAC.1996.545563
