Title :
Power reduction in test-per-scan BIST
Author :
Zhang, Xiaodong ; Roy, Kaushik
Author_Institution :
Synopsys Inc., Mountain View, CA, USA
Abstract :
The input signal activities during test can be much higher than during test. Hence, it is important to reduce power consumption to avoid any failures during test. In this paper, we propose techniques to reduce power dissipations in both the combinational block and the scan chain for test-per-scan BIST. Some extra circuitry is introduced between the combinational logic and the scan chain to make the combinational block idle during the scan-in and scan-out operation, and the scan chain is re-ordered so that the number of signal transitions in it is minimized. Compared to the standard weighted random pattern (WRP) testing (without re-ordering), the number of signal transitions in the scan chain can be reduced by 43.8%. With some extra circuitry, the power dissipation in the combinational block can be reduced to less than 0.86%, compared to the standard test-per-scan BIST
Keywords :
built-in self test; combinational circuits; design for testability; digital integrated circuits; integrated circuit testing; logic testing; low-power electronics; probability; sequential circuits; DFT; combinational block; combinational logic; power consumption; power reduction; scan chain reordering; signal transitions minimization; test-per-scan BIST; Built-in self-test; CMOS logic circuits; CMOS technology; Capacitance; Circuit faults; Circuit testing; Clocks; Combinational circuits; Power dissipation; Sequential analysis;
Conference_Titel :
On-Line Testing Workshop, 2000. Proceedings. 6th IEEE International
Conference_Location :
Palma de Mallorca
Print_ISBN :
0-7695-0646-1
DOI :
10.1109/OLT.2000.856625
