Power reduction in test-per-scan BIST

The input signal activities during test can be much higher than during test. Hence, it is important to reduce power consumption to avoid any failures during test. In this paper, we propose techniques to reduce power dissipations in both the combinational block and the scan chain for test-per-scan BIST. Some extra circuitry is introduced between the combinational logic and the scan chain to make the combinational block idle during the scan-in and scan-out operation, and the scan chain is re-ordered so that the number of signal transitions in it is minimized. Compared to the standard weighted random pattern (WRP) testing (without re-ordering), the number of signal transitions in the scan chain can be reduced by 43.8%. With some extra circuitry, the power dissipation in the combinational block can be reduced to less than 0.86%, compared to the standard test-per-scan BIST