A novel instruction scheduling scheme for clustered VLIW architecture

The availability of potentially high operation concurrency in various applications has led to the development of VLIW Processors. To reduce the complexity at hardware and power consumption, the instruction scheduling is done statically. The disadvantage of long wires in the VLIW architecture was overcome by clustering of the processors (Eg. TMS320c6000 series). In clustered VLIW processors, the execution units are grouped to different clusters and the register usage is restricted within the clusters except through the inter-cluster communication slots. So for such architectures, the instruction scheduling has become complex. This work proposes an integrated instruction partitioning and scheduling technique for clustered VLIW architectures. The scheduling algorithm is a modified list scheduling algorithm which uses the amount of clock cycles followed by each instruction and the number of successors of an instruction to prioritise the instructions. The partitioning phase assigns each instruction a cluster depending upon the cluster in which the parent instructions are scheduled. The method produces a better schedule when compared to the list scheduling technique.