• DocumentCode
    2235603
  • Title

    CORPS-a pipelined fair packet scheduler for high speed switches

  • Author

    Cavendish, Dirceu

  • Author_Institution
    C&C Res. Labs., NEC Res. Inst., Princeton, NJ, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    55
  • Lastpage
    64
  • Abstract
    Input queues have become an attractive switch architecture, since it was shown that a throughput of up to 100% is achievable when a virtual output queue (VOQ) is used. Although schedulers for VOQ switches have been proposed, pipelined schedulers, whose processing requirements increase at most linearly with line speeds, have not yet matured. We introduce CORPS, a pipelined scheduler which allows fair scheduling among input lines of a crossbar high speed switch fabric. By means of a round-robin communication scheme, CORPS achieves scalability to a large number of ports. Moreover, CORPS achieves one scheduling decision per line per slot, by scheduling packets into future slots. The tradeoffs involved are packet delay and utilization
  • Keywords
    delays; packet switching; pipeline processing; queueing theory; telecommunication traffic; CORPS; VOQ switches; approximate analysis; crossbar high speed switch fabric; discrete event simulation; distributed architecture; high speed switches; input lines; input queues; line speeds; packet delay; pipelined fair packet scheduler; processing requirements; round-robin communication; scalability; switch architecture; throughput; uniform traffic analysis; utilization; virtual output; Communication switching; Fabrics; Laboratories; Message passing; National electric code; Packet switching; Scalability; Scheduling algorithm; Switches; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High Performance Switching and Routing, 2000. ATM 2000. Proceedings of the IEEE Conference on
  • Conference_Location
    Heidelberg
  • Print_ISBN
    0-7803-5884-8
  • Type

    conf

  • DOI
    10.1109/HPSR.2000.856647
  • Filename
    856647