Novel Data dependent pausible clocking scheme with pll calibration for GALS NOC

Asynchronous design offers an attractive solution to overcome the problems faced by Networks-on-Chip (NoC) designers such as timing constraints. GALS Asynchronous NoCs requires efficient calibrated clocking scheme which has minimum drift, independent of Process Voltage Temperature(PVT), use minimum static and dynamic power. Clocking scheme should enable smooth synchronization among different clock domain. This paper first presents novel data dependent Pausible clocking scheme with Phase lock loop calibration. It calibrate for phase alignment. Local Clock is calibrated with reference clock generated from reference clock source with PLL mode for the desired frequency which is set with dealylined. This aligned local clock will use for clocking of synchronous module which is wrapped with asynchronous wrapper. It helps in avoiding metastability during crossing of data from one clock domain to another clock domain. Here we present the Petri net models of the Globally Asynchronous and Locally Synchronous(GALS) architectures for speed independent (SI). The models are feed into Petrify to produce logic equations for gate level implementation of asynchronous circuit. The synchronous and asynchronous circuits are implemented on technology of saed90nm provided with Synopsys university program. Simulation is carried on VCS of Synopsys and synthesis on design compiler.