Title :
Cycle time reduction program at ACL
Author :
Boebel, F.G. ; Ruelle, O.
Author_Institution :
Siemens SA, Corbeil-Essonnes, France
Abstract :
In this paper we focus on the results of the DRAM production cycle time team with special emphasis on: how does CT translate into productivity; what tools are needed for effective CT analysis including daily going rate (DGR) issues; how to find and how to fight the main CT detractors The results are compared with the real world execution at the SIEMENS/IBM Advanced CMOS line (ACL) in Essonnes-Corbeil
Keywords :
CMOS memory circuits; DRAM chips; human resource management; integrated circuit manufacture; production control; ACL; CT analysis; DRAM production; Siemens/IBM advanced CMOS line; cycle time reduction; daily going rate; productivity; Costs; Data mining; Job shop scheduling; Logistics; Manufacturing; Mass production; Productivity; Random access memory; Semiconductor device manufacture; Testing;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1996. ASMC 96 Proceedings. IEEE/SEMI 1996
Conference_Location :
Cambridge, MA
Print_ISBN :
0-7803-3371-3
DOI :
10.1109/ASMC.1996.557990
