Communication Architectures for Run-Time Reconfigurable Modules in a 2-D Mesh on FPGAs

This paper examines the feasibility of utilizing a 2-dimensional (2-D) mesh of run-time reconfigurable modules (RTRMs) on a dynamically and partially reconfigurable (DPR) FPGA for throughput- and real-time-driven tasks. To utilize a 2-D mesh of RTRMs, efficient communication architectures (CA) are required, which will be presented in this work. Such a 2-D mesh of RTRMs on a DPR-capable FPGA can be utilized for throughput-driven tasks to dynamically offload compute functions on a host coupled system, providing multi-user and multi-context execution on behalf of user demands. For embedded systems, it can be utilized as a highly dynamical platform by providing functional enhancement by module replacement during run-time. The exploration also includes a CA for real-time communication between RTRMs in a 2-D mesh. The presented CA design is based on a novel methodology by applying run-time reconfiguration to increase the performance. The design, the implementation, the performance and the resource utilization is shown for throughput- and real-time-driven CAs. As proof of concept, a case study is conducted for the presented CAs on state of the art Virtex-5 FPGAs.