A new digit-serial systolic multiplier for finite fields GF(2m )

This paper presents a new digit-serial systolic multiplier for finite fields GF(2^m). The hardware requirements of the proposed multiplier are less than those of the existing multiplier of the same class, while maintaining the same cell delay. The proposed multiplier possesses the features of regularity, modularity, and unidirectional data flow. Thus, it is well suited to VLSI implementation. If the proposed digit-serial multiplier chooses the digit size L appropriately, it can meet the throughput requirement of a certain application with minimum hardware