Architecture and application partitioning for reconfigurable system design

Author

Ben Chehida, K. ; Auguin, M. ; Raimbault, S.

Author_Institution

I3S, Univ. of Nice Sophia Antipolis, Nice, France

fYear

2002

fDate

3-6 Sept. 2002

Firstpage

1

Lastpage

4

Abstract

This paper presents a Genetic Algorithm (GA) based approach for Hardware/Software partitioning targeting an architecture composed of a processor and a dynamically reconfigurable datapath (FPGA). From an acyclic task graph and a set of Area-Time implementation trade offs points for each task, our GA performs HW/SW partitioning and scheduling such that the global application execution time is minimized. The efficiency of our GA is established through its application to a AC-3 decoder function and its performance is compared with a greedy algorithm.

Keywords

field programmable gate arrays; genetic algorithms; graph theory; integrated circuit design; microprocessor chips; minimisation; processor scheduling; reconfigurable architectures; AC-3 decoder function; FPGA; acyclic task graph; application partitioning; architecture partitioning; area time implementation trade offs points; genetic algorithm based approach; global application execution time minimization; hardware-software partitioning; hardware-software scheduling; reconfigurable datapath; reconfigurable system design; Abstracts; Algorithm design and analysis; Clustering algorithms; Genetics; Heuristic algorithms; Partitioning algorithms; System analysis and design;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Conference, 2002 11th European

Conference_Location

Toulouse

ISSN

2219-5491

Type

conf

Filename

7072102