A level shifter for deep-submicron node using multi-threshold technique

Shrinking of devices to deep sub micron technology have shifted focus of the VLSI CMOS chip circuit designers to new design issues such as sub threshold leakages, reduction of supply voltage and threshold voltages, DIBL (Drain induced Barrier lowering), leakage currents and speed optimization. The transistors at lower channel length show deviation to characteristics such as threshold variation, sub-threshold leakage currents and DIBL. This paper proposes a new voltage level shifter circuit to overcome leakage currents in short channel-devices and can save power up to 17-32% of power consumption compared to dual Vdd conventional level shifter. In this paper we present and analyze the simulation results of the proposed level shifter operated at 100 MHZ frequency. These results for delay, power and leakage current are obtained by varying load capacitance. The circuit is simulated using 0.18μm technology.