DocumentCode :
2236571
Title :
A full section overhead processing chip set for 10 Gbit/s SDH-based optical fiber transmission system
Author :
Lee, Tae-Hee ; Cho, Jae-II ; Ko, Jeong-Hoon
Author_Institution :
Electron. & Telecommun. Res. Inst., Taejon, South Korea
fYear :
1997
fDate :
9-12 Sep 1997
Firstpage :
1143
Abstract :
A full section overhead (SOH) processing chip set has been designed for use in a 10 Gbit/s SDH-based optical fiber transmission system. The chip set has been fabricated in a 0.6 μm CMOS and GaAs gate array technology. The features supported by the chip set include STM-64 SOH insertion and extraction including regenerator section trace (RST), frame alignment word insertion and detection, 32-bit parallel scrambling and descrambling, 8:1 multiplexing and demultiplexing, alarm detection and generation, and performance monitoring. This paper introduces a novel multiplexing and demultiplexing structure for a parallel processing of the STM-64 signal using the chip set. This paper also describes the architecture of the chip set, and several of the chip set´s more interesting features
Keywords :
III-V semiconductors; MESFET integrated circuits; application specific integrated circuits; cryptography; demultiplexing equipment; digital signal processing chips; gallium arsenide; integrated circuit design; logic arrays; multiplexing equipment; optical communication equipment; optical fibre communication; parallel architectures; synchronous digital hierarchy; 0.6 micron; 10 Gbit/s; 10 Gbit/s SDH-based optical fiber transmission system; 32 bit; 32-bit parallel scrambling; 8:1 multiplexing; CMOS; GaAs; GaAs gate array technology; STM-64 SOH insertion; alarm detection; demultiplexing; demultiplexing structure; descrambling; detection; extraction; frame alignment word insertion; full section overhead processing chip set; generation; multiplexing structure; parallel processing; performance monitoring; regenerator section trace; Demultiplexing; Gallium arsenide; Gold; Monitoring; Optical fibers; Parallel processing; Payloads; Power dissipation; Signal processing; Synchronous digital hierarchy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information, Communications and Signal Processing, 1997. ICICS., Proceedings of 1997 International Conference on
Print_ISBN :
0-7803-3676-3
Type :
conf
DOI :
10.1109/ICICS.1997.652161
Filename :
652161
Link To Document :
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