Multidimensional loop fusion for low-power

Development of semiconductor technology has led to advent of complex digital systems, such as portable, embedded, SoCs, and FPGA devices. Complexity of modern applications and deep-submicron technologies make low-power design attitude compulsory. The higher the level of abstraction of a design that power optimizations are applied, the higher are potential savings. Memory is known to be extremely power consuming. A new technique of loop fusion to optimize a behavioral description of an application before the hardware/software partitioning is presented in this paper.