Waferside Analysis Technique for GaAs-Based Circuits

Analyzing the root-cause of GaAs-based device failures often involves an elaborate process of delayering and/or cross-sectioning to study the failure sites. This paper introduces an innovative analytical approach by looking through the waferside of a circuit thereby gaining access to the underside of the elements of interest. This technique allows a clear view of the underside of the process thus expanding its usefulness in general failure analysis.