Accelerating 2D FFT with Non-Power-of-Two Problem Size on FPGA

The emergence of embedded and multimedia applications, which have a data-centric favor to them, have great influences on the design methodology of future systems. The 2D FFT is of particular importance to these applications. In this paper, leveraging the reconfigurable features of off-the-shelf FPGAs, we propose a stream architecture that is suitable for accelerating 2D FFT with variable and non-power-of-two problem size. The system is built upon the concept of coarse-grained and application-specific pipeline and is optimized for 2D and real data FFT specifically. Separating data flow from computing flow and providing hardware support for data flow permutation involved in 2D FFT, our design outperforms previous work by 1:8 21 times. Moreover, when facing real data, the speed will further increase by nearly 100%. To increase designer productivity, we reinforced traditional HDL-based hardware design flow with High-Level Synthesis concept. The prototyping system on a customized FPGA-based accelerator card can operate in 200MHz stably.