Title :
Parallel Data Sort Using Networked FPGAs
Author :
Singaraju, Janardhan ; Chandy, John A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Connecticut, Storrs, CT, USA
Abstract :
We present an approach to perform transformation and reduction data operations in an intelligent network switch comprised of FPGAs. Data processing in a distributed system often requires the data to be aggregated at a single client before performing the data operation. Performing data processing in the interconnection network which has the global view of the data could speed up the application. In this paper, we show an example of a data sorting application that uses parallel servers to pre-sort data and then uses FPGAs within the switch to merge sort data as it passes through the network thereby reducing computation requirements at the client node. The architecture takes advantage of the NetFPGA board to perform a 4-way merge sort in an embedded network FPGA device. Using this architecture we show how data sort times can be reduced significantly.
Keywords :
data acquisition; data reduction; field programmable gate arrays; file servers; interconnections; merging; sorting; FPGA; data aggregation; data processing; data reduction; distributed system; intelligent network switch; interconnection network; merge sort data; parallel servers; pre-sort data;
Conference_Titel :
Reconfigurable Computing and FPGAs (ReConFig), 2010 International Conference on
Conference_Location :
Quintana Roo
Print_ISBN :
978-1-4244-9523-8
Electronic_ISBN :
978-0-7695-4314-7
DOI :
10.1109/ReConFig.2010.85