Abstract :
The following topics are dealt with: optimized constraint logic programming-based propagation sequence generation; CMOS sequential standard cells; microprocessor coverage-directed verification; statecharts FPGA implementation; low-power multidimensional loop fusion; timing-driven placement algorithm; digital PLL lock detector; SoC memory faulty cells; vector-logical diagnosis method; system level hardware design; NoC architecture reliability; in-circuit testing; floor planning; routing techniques; and Petri Nets.
Keywords :
CMOS logic circuits; Petri nets; constraint handling; digital phase locked loops; digital storage; fault diagnosis; field programmable gate arrays; integrated circuit layout; integrated circuit reliability; integrated circuit testing; low-power electronics; microprocessor chips; network routing; network-on-chip; sequential circuits; timing; CMOS sequential standard cells; FPGA implementation; NoC architecture reliability; Petri Nets; SoC memory faulty cells; constraint logic programming; digital PLL lock detector; floor planning; in-circuit testing; low-power multidimensional loop fusion; microprocessor coverage-directed verification; routing techniques; sequence generation; system level hardware design; timing-driven placement algorithm; vector-logical diagnosis; Analytical models; Hardware; Predictive models; Process control; Software; System-on-a-chip; Testing;
Conference_Titel :
Design & Test Symposium (EWDTS), 2008 East-West
Conference_Location :
Lviv
Print_ISBN :
978-1-4244-3402-2
DOI :
10.1109/EWDTS.2008.5580163
