Bringing C++ productivity to VHDL world: From language definition to a case study

During the last years the hardware description languages evolved providing a faster and a more generic way of describing synthesizable hardware architectures. E.g., VHDL 2008 extended the concept of generics from integral numbers to types, packages and subroutines. This paper presents a hardware description language based on the VHDL semantics - THDL++. It supports the extended generic concept and improves it further by supporting compile-time lists with “for each” semantics, inheritance, expression type derivation and late binding. We also present THDL++ compiler with 2 back-ends: a synthesizable VHDL-87 back-end makes it easy to integrate THDL++ into any existing design flow, and a C++ back-end that generates a cycle-accurate model for fast simulation. We illustrate how using THDL++ significantly reduces design effort compared to raw VHDL by making the code more readable and reusable. As a case study, we present a hardware LZSS (ZIP) compressor, targeting Xilinx FPGAs that´s development was accelerated by using THDL++. We demonstrate how using THDL++ reduced the amount of code lines by a factor of 1.85 compared to VHDL and how using the C++ back-end increased simulation performance by a factor of 8 compared to ModelSim [1]. The THDL++ compiler and an IDE integrated with Xilinx toolchain is available online [2].