Impacts of wire-LER on Nanowire MOSFET devices, subthreshold SRAM and logic circuits

We propose a methodology to simulate realistic 2D Line Edge Roughness (LER) pattern for NanoWire (NW) MOSFETs in TCAD platform. This approach predicts the device characteristic and variations including V_th, I_on and Subthreshold Swing (S.S.) fluctuations more accurately compared with prior literature considering two types of primarily 1D NW geometry variation [1]. Based on the proposed simulation approach, we carry out a comprehensive analysis using 3D atomistic TCAD and mixed-mode Monte Carlo simulations on the impacts of Wire-LER on the variability of NW MOSFET device characteristics, stability of 6T SRAM operating in subthreshold region and logic circuits. The results are extensively compared with previous approaches to illustrate the deficiency of modeling and predictions based on 1D NW geometry variation.