Title :
R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip
Author :
Devaux, Ludovic ; Pillement, Sebastien ; Chillet, Daniel ; Demigny, Didier
Author_Institution :
IRISA, Univ. of Rennes I, Lannion, France
Abstract :
The use of dynamically and partially reconfigurable resources permits to support complex applications. If dynamic and partial reconfiguration offers new possibilities for applicative implementations, it could also provide new ways to design efficient interconnection architectures. In this way, R2NoC, a Network on Chip constituted of dynamically reconfigurable routers is presented. First characterizations of this network are provided through the physical implementation of one single router in a modern FPGA.
Keywords :
field programmable gate arrays; multiprocessor interconnection networks; network routing; network-on-chip; reconfigurable architectures; FPGA; R2NoC; interconnection architecture; networks on chip; partial reconfiguration; reconfigurable router; NoC; R2NoC; dynamic reconfiguration; fat-tree;
Conference_Titel :
Reconfigurable Computing and FPGAs (ReConFig), 2010 International Conference on
Conference_Location :
Quintana Roo
Print_ISBN :
978-1-4244-9523-8
Electronic_ISBN :
978-0-7695-4314-7
DOI :
10.1109/ReConFig.2010.35
