A multiscale morphological coprocessor for low-power face authentication

This paper reports a low-power multiscale morphological coprocessor for mobile face authentication devices. In such a system, face verification is performed by extracting mathematical morphology features (erosions and dilations) using a set of structural elements of increasing size. The proposed architecture reduces the number of operations by reusing results, and lowers the amount of needed memory transfers by caching data locally. To improve processing speed at a given operating frequency, four morphological units operate in parallel. Structuring elements can be modified easily as they are described in a table. The architecture was validated using an in-house developed tool, the corresponding simulation results being presented at the end of the paper.