Implementation of a 4.8 Kbps CELP speech coder on a TMS320C44 processor board

Author

Teo, T.T. ; Tan, E.C. ; Kwoh, C.K.

Author_Institution

Sch. of Appl. Sci., Comput. Eng., Nanyang Technol. Univ., Singapore

fYear

1997

fDate

9-12 Sep 1997

Firstpage

1168

Abstract

The CELP algorithm has been used in the standardization of the Federal Standard FS-1016 speech codec in 1991. Over the years, much research effort results in many variants of CELP with optimization in the computation time, codebook structures and search strategies. This paper presents the implementation of a 4.8 Kbps code excited linear prediction speech coder using the TMS320C44 digital signal processor. The emphasis is on exploiting the DSP hardware platform

Keywords

digital signal processing chips; linear predictive coding; speech codecs; speech coding; 4.8 Kbit/s; CELP algorithm; CELP speech coder; DSP hardware platform; Federal Standard FS-1016; TMS320C44 digital signal processor; TMS320C44 processor board; codebook structures; computation time; search strategies; software structure; speech codec; standardization; Decoding; Digital signal processing; Digital signal processors; Hardware; Random access memory; Read-write memory; Signal processing algorithms; Speech codecs; Speech processing; Standardization;

fLanguage

English

Publisher

ieee

Conference_Titel

Information, Communications and Signal Processing, 1997. ICICS., Proceedings of 1997 International Conference on

Print_ISBN

0-7803-3676-3

Type

conf

DOI

10.1109/ICICS.1997.652166

Filename

652166