Title :
Parallel positive justification in SDH C-4 mapping
Author :
Shiwen, Mao ; Xiaokang, Lin ; Fuqiang, Shi
Author_Institution :
Tsinghua Univ., Beijing, China
Abstract :
Bit rate justification is a key technique in digital multiplexing. SDH adopts positive justification for C-4 mapping and positive/zero/negative justification for other mappings. The mapping of C-4 has the highest system frequency in all bit rate justifications of SDH. This demands highly on the technology and power consumption in the ASIC design. This paper puts forward a novel technique of positive justification with parallel processing and solves the problem caused by high speed. This method is very useful for implementing the C-4 mapping with CMOS gate array technology. The design has been implemented with FPGAs of Xilinx Inc. The paper ends with the mapping jitter test results, which are quite satisfied
Keywords :
CMOS logic circuits; application specific integrated circuits; field programmable gate arrays; jitter; parallel processing; synchronisation; synchronous digital hierarchy; ASIC design; CMOS gate array technology; FPGA; Parallel positive justification; SDH C-4 mapping; Xilinx; bit rate justification; digital multiplexing; mapping jitter test results; parallel processing; positive/zero/negative justification; Application specific integrated circuits; Bit rate; CMOS technology; Energy consumption; Field programmable gate arrays; Frequency; Jitter; Parallel processing; Synchronous digital hierarchy; Testing;
Conference_Titel :
Communications, 1997. ICC '97 Montreal, Towards the Knowledge Millennium. 1997 IEEE International Conference on
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7803-3925-8
DOI :
10.1109/ICC.1997.595053
