Title :
Which is cooler, trench or multi-epitaxy? Cutting edge approach for the silicon limit by the super trench power MOS-FET (STM)
Author :
Minato, T. ; Nitta, T. ; Uenisi, A. ; Yano, M. ; Harada, M. ; Hine, S.
Author_Institution :
ULSI Dev. Center, Mitsubishi Electr. Corp., Kumomoto, Japan
Abstract :
STM structure makes it possible to break through the Si limit via new RESURF effect in very tight periodic p and n columns repetition by using deep trench technology and trench sidewall ion implantation. In a wide breakdown voltage range from 200 to 1000 V, STM also gives greatly improved electrical characteristics at the cost of only one extra mask step in the DMOS fabrication wafer process procedure
Keywords :
buried layers; power MOSFET; semiconductor epitaxial layers; 200 to 1000 V; DMOS fabrication wafer process procedure; RESURF effect; STM structure; Si; Si limit; deep trench technology; multi-epitaxy; super trench power MOSFET; trench; trench sidewall ion implantation; wide breakdown voltage range; Boundary conditions; Costs; Electric variables; Epitaxial growth; Fabrication; Ion implantation; Low voltage; Periodic structures; Silicon; Tail;
Conference_Titel :
Power Semiconductor Devices and ICs, 2000. Proceedings. The 12th International Symposium on
Conference_Location :
Toulouse
Print_ISBN :
0-7803-6269-1
DOI :
10.1109/ISPSD.2000.856776
