Title :
A novel hybrid memory architecture with parallel DRAM for fast packet buffers
Author_Institution :
Inst. of Commun. Networks & Comput. Eng. (IKR), Univ. of Stuttgart, Stuttgart, Germany
Abstract :
High speed Internet routers and switches require fast packet buffer to hold packets during times of congestion. These buffers usually use a memory hierarchy that consist of expensive but fast SRAM and cheap but slow DRAM to meet both, speed and capacity requirements. A challenge building these packet buffers is to provide deterministic bandwidth guarantee under any traffic condition. We propose a novel hybrid packet buffer architecture with parallel DRAMs. Our approach reduces the amount of required SRAM compared to state-of-the-art architectures significantly, e. g., the tail SRAM by 47% for a 100Gbps line card using DDR3 SDRAM. Our architecture also applies packet aggregation and thereby minimizes the required DRAM and SRAM bandwidth and eliminates fragmentation. We are currently implementing the architecture on an FPGA and provide first results.
Keywords :
DRAM chips; Internet; SRAM chips; buffer storage; field programmable gate arrays; memory architecture; telecommunication network routing; DDR3 SDRAM; DRAM bandwidth; FPGA; Internet router; SRAM bandwidth; fast packet buffer; hybrid memory architecture; hybrid packet buffer architecture; packet aggregation; parallel DRAM; Bandwidth; Memory management; Resource management; Round robin; SDRAM;
Conference_Titel :
High Performance Switching and Routing (HPSR), 2010 International Conference on
Conference_Location :
Richardson, TX
Print_ISBN :
978-1-4244-6969-7
Electronic_ISBN :
978-1-4244-6970-3
DOI :
10.1109/HPSR.2010.5580282