Implant spacer optimization for the improvement of power MOSFETs´ unclamped inductive switching (UIS) and high temperature breakdown

Author

Kocon, Christopher ; Zeng, Jun ; Stokes, Rick

Author_Institution

Intersil Corp., Mountaintop, PA, USA

fYear

2000

fDate

2000

Firstpage

157

Lastpage

160

Abstract

This paper proposes an improvement to a 30 V N-Channel Power VDMOSFET´s UIS and high temperature breakdown voltage capability by using a non-etched 0.0750 μm thin oxide spacer as masking for a high dose body implant in lieu of a power industry accepted 0.3 μm-0.5 μm etched spacer. This thinner non-etched spacer allows for a more highly concentrated and precise body dopant distribution beneath the source region, for a given implant energy, preventing the parasitic BJT from turning on at high current densities. As a consequence the UIS and high temperature (⩾150°C) breakdown characteristics are enhanced without increasing threshold voltage or device on-resistance

Keywords

doping profiles; high-temperature electronics; ion implantation; masks; optimisation; power MOSFET; semiconductor device breakdown; semiconductor device measurement; semiconductor doping; 0.0750 mum; 150 C; 30 V; N-channel power VDMOSFET; high current densities; high dose body implant; high temperature breakdown; high temperature breakdown voltage capability; implant spacer optimization; masking; on-resistance; parasitic BJT; power MOSFET; precise body dopant distribution; source region; threshold voltage; unclamped inductive switching; unetched thin oxide spacer; Body regions; Boron; Breakdown voltage; Doping; Etching; Immune system; Implants; MOSFET circuits; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2000. Proceedings. The 12th International Symposium on

Conference_Location

Toulouse

ISSN

1063-6854

Print_ISBN

0-7803-6269-1

Type

conf

DOI

10.1109/ISPSD.2000.856795

Filename

856795