Title :
Physical compact modeling of layout dependent metal resistance in integrated LDMOS power devices
Author :
Kniffin, Margaret L. ; Thoma, Rainer ; Victory, James
Author_Institution :
Digital DNA Labs., Motorola Inc., Tempe, AZ, USA
Abstract :
Including the effects of parasitic metal resistance and their dependence on device layout is crucial to accurate modeling of large area LDMOS devices. This paper presents the derivation and use of compact analytical model equations for accurately predicting the Rdson performance of large area LDMOS devices. Results are compared with both numerical simulations and experimental measurements
Keywords :
MOS integrated circuits; electrical resistivity; integrated circuit layout; integrated circuit modelling; power MOSFET; power integrated circuits; semiconductor device models; Rdson performance; compact analytical model equations; device layout; integrated LDMOS power devices; large area LDMOS devices; layout dependent metal resistance; numerical simulation; parasitic metal resistance; physical compact modelling; Analytical models; Circuit simulation; Computational modeling; Electrical resistance measurement; Equations; Laboratories; Numerical simulation; Performance analysis; Power measurement; Resistors;
Conference_Titel :
Power Semiconductor Devices and ICs, 2000. Proceedings. The 12th International Symposium on
Conference_Location :
Toulouse
Print_ISBN :
0-7803-6269-1
DOI :
10.1109/ISPSD.2000.856799
