An O(n) algorithm for transistor stacking with performance constraints

We describe a new constraint-driven stacking algorithm for diffusion area minimization of CMOS circuits. It employs an Eulerian trail finding algorithm that can satisfy analog-specific performance constraints. Our technique is superior to other published approaches both ill terms of its time complexity and in the optimality of the stacks it produces. For a circuit with n transistors. The time complexity is O(n). All performance constraints are satisfied and, for a certain class of circuits, optimum stacking is guaranteed